Data communication speeds in electronic systems continue to increase well into multiple Gbps (gigabits per second). Such speeds are prevalent in systems deploying serial data communication PHYs (physical layers) and in standards that include physical layer specifications (e.g., PCIe1/2/3, SATA 1/2/3, GbE, XAUI/2xXAUI, 10GBase-KR, Interlaken, USB 2/3, etc.) as well as in memory data standards for interfaces (e.g., DDR3, DDR4, LPDDR3, LPDDR4, etc.). At these speeds, clock and data recovery (CDR) circuitry is required to accurately (with low bit-error rate) recover the received data. Many CDR circuits include phase interpolators to enable adjustment of the phase of the clock or clocks used to sample or re-time the incoming data stream.
Unfortunately, legacy phase interpolators have limited capabilities. As data speeds increase and power budgets decrease in electronic systems, particularly in mobile or battery-powered applications, circuits must also scale to lower power consumption levels and accommodate more sophisticated power management schemes that deploy lower supply voltages, increased power state switching. Such circuits may be subjected to the presence of relatively higher power supply noise. Legacy phase interpolators have not scaled with today's power requirements both in terms of power consumption and power supply rejection (PSR). Further, legacy phase interpolators do not exhibit highly linear interpolation between phases, which limits phase adjustment accuracy and can be insufficient for higher speed data. Legacy phase interpolators are also limited in the frequency range over which the interpolator can be used, in turn limiting the re-use of the core design which is critical in today's fast time-to-market and cost sensitive electronics industry. Still worse, legacy phase interpolators deploy complicated phase and duty cycle adjustment techniques that require significant integrated circuit area and potentially longer calibration and test times.
Techniques are needed to address the problem of implementing a low power phase interpolator that exhibits high power supply rejection, highly linear interpolation, over a wide frequency range, and exhibiting low cost duty cycle distortion.
None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed high performance phase interpolators. Therefore, there is a need for improvements.